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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11447-1E
MEMORY Mobile FCRAMTM
CMOS
64M Bit (4 M word x 16 bit)
Mobile Phone Application Specific Memory
MB82DP04184E-65L
DESCRIPTION
The Fujitsu MB82DP04184E is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous Static Random Access Memory (SRAM) interface containing 67,108,864 storages accessible in a 16-bit format. This MB82DP04184E is suited for mobile applications such as Cellular Handset and PDA. *: FCRAM is a trademark of Fujitsu Limited, Japan.
FEATURES
Asynchronous SRAM Interface Fast Access Time : tAA = tCE = 65 ns Max 8 words Page Access Capability : tPAA = 20 ns Max Low Voltage Operating Condition : VDD = 2.6 V to 3.1 V Wide Operating Temperature : TA = 0 C to + 70 C Byte Control by LB and UB Low Power Consumption : IDDA1 = 40 mA Max IDDS1 = 200 A Max * Various Power Down mode : Sleep 8M-bit Partial 16M-bit Partial * Shipping Form : Wafer, Chip, 71-ball plastic FBGA * * * * * * *
MAIN SPECIFICATIONS
Parameter Access Time (Max) (tCE, tAA) Active Current (Max) (IDDA1) Standby Current (Max) (IDDS1) Power Down Current (Max) (IDDPS) MB82DP04184E-65L 65 ns 40 mA 200 A 10 A
Copyright(c)2007 FUJITSU LIMITED All rights reserved
MB82DP04184E-65L
PIN ASSIGNMENT
(TOP VIEW)
A B C D E F G H J K L M
8 7 6 5 4 3 2 1
NC NC
NC NC A11 A8 WE DU LB
A15 A12 A19 CE2 DU UB A6 A3
A21 A13 A9 A20 DU A18 A5 A2
NC A14 A10
A16 NC DQ6
NC DQ15
VSS DQ7 DQ14 DQ5 NC DQ11 DQ2 DQ8
NC NC
NC NC
DQ13 DQ12 DQ4 DQ3 VDD VDD DQ10 DQ0 CE1
A17 A4 A1
DQ1 VSS A0
DQ9 OE NC
NC NC NC
A7
NC NC
NC NC
(BGA-71P-M03)
PIN DESCRIPTION
Pin Name A21 to A0 CE1 CE2 WE OE LB UB DQ7 to DQ0 DQ15 to DQ8 VDD VSS NC Address Input Chip Enable 1 (Low Active) Chip Enable 2 (High Active) Write Enable (Low Active) Output Enable (Low Active) Lower Byte Control (Low Active) Upper Byte Control (Low Active) Lower Byte Data Input/Output Upper Byte Data Input/Output Power Supply Voltage Ground No Connection Description
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MB82DP04184E-65L
BLOCK DIAGRAM
VDD VSS
A21 to A0
Address Latch & Buffer
Row Decoder
Memory Cell Array 67,108,864 bits
DQ7 to DQ0
I/O Data Buffer
DQ15 to DQ8
Input Data Latch & Control
Sense/Switch
Output Data Control
Column Decoder
Address Latch & Buffer
CE2
Power Control
CE1 WE LB UB OE
Timing Control
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MB82DP04184E-65L
FUNCTION TRUTH TABLE
Mode Standby (Deselect) Output Disable*1 Output Disable (No Read) Read (Upper Byte) H Read (Lower Byte) Read (Word) No Write Write (Upper Byte) L Write (Lower Byte) Write (Word) Power Down*2 L X X X H*4 L L X H L X Valid Valid X Input Valid Invalid H L L L L H H H L H L Valid Valid Valid Valid CE2 H CE1 H WE X H OE X H LB X X H H UB X X H L A21 to A0 X *3 Valid Valid DQ7 to DQ0 High-Z High-Z High-Z High-Z Output Valid Output Valid Invalid Invalid DQ15 to DQ8 High-Z High-Z High-Z Output Valid High-Z Output Valid Invalid Input Valid
Input Valid Input Valid High-Z High-Z
Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High impedance *1 : Should not be kept this logic condition longer than 1 s. *2 : Power Down mode can be entered from standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down program. Refer to " POWER DOWN" for the detail. *3 : Can be either VIL or VIH but must be valid before read or write. *4 : OE can be VIL during write operation if the following conditions are satisfied; (1) Write pulse is initiated by CE1. Refer to "(12) Read/Write Timing 1-1 (CE1 Control)" in " TIMING DIAGRAMS". (2) OE stays VIL during write cycle.
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MB82DP04184E-65L
POWER DOWN
* Power Down The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in Power Down mode and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from Power Down mode. This device has three Power Down modes, Sleep, 8M-bit Partial and 16M-bit Partial. The selection of Power Down mode can be programmed by series of read/write operation. Each mode has following data retention features. Mode Data Retention Retention Address Sleep (default) 8M-bit Partial 16M-bit Partial No 8M bits 16M bits N/A 000000h to 07FFFFh 000000h to 0FFFFFh
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to program to Sleep mode after power-up. * Power Down Program Sequence The program requires total six read/write operations with unique address and data. The device should be in standby mode in the interval between each read/write operation. The following table shows the detail sequence. Cycle # Operation Address Data 1st 2nd 3rd 4th 5th 6th Read Write Write Write Write Write 3FFFFFh (MSB) 3FFFFFh 3FFFFFh 3FFFFFh 3FFFFFh 3FFFFFh Read Data (RDa) RDa RDa FFFFh Data Key FFFFh
The first cycle is to read from most significant address (MSB). The second and third cycles are to write to MSB. If the second or third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. It is recommended to write back the data (RDa) read by first cycle to MSB in order to secure the data. The fourth to sixth cycles are to write to MSB. The data of fourth and sixth cycles must be "FFFFh" and data of fifth cycle are specific data key for mode selection. If the fourth to sixth cycles are written into different address, the program is also cancelled but write data may not be written as normal write operation. Once this program sequence is performed from a Partial mode to the other Partial mode, the written data stored in memory cell array may be lost. Therefore, this program should be performed prior to regular read/write operation if Partial Power Down mode is used. * Data Key The data key has following format. Mode Sleep (default) 8M-bit Partial 16M-bit Partial Data DQ15 to DQ2 1 1 1 DQ1 1 0 0 DQ0 1 1 0 Hexadecimal FFFFh FFFDh FFFCh 5
MB82DP04184E-65L
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage of VDD Supply Relative to VSS* Voltage at Any Pin Relative to VSS* Short Circuit Output Current Storage Temperature * : All voltages are referenced to VSS. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VDD VIN, VOUT IOUT TSTG Value Min - 0.5 - 0.5 - 50 - 55 Max + 3.6 + 3.6 + 50 + 125 Unit V V mA
o
C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage*1 Input High Voltage * * Ambient Temperature
1, 2
Symbol VDD VSS VIH VIL TA
Value Min 2.6 0 VDD x 0.8 - 0.3 0 Max 3.1 0 VDD + 0.2 VDD x 0.2 + 70
Unit V V V V C
Input Low Voltage *1, *3
*1 : All voltages are referenced to VSS. *2 : Maximum DC voltage on input and I/O pins are VDD + 0.2 V. During voltage transitions, inputs may overshoot to VDD + 1.0 V for periods of up to 5 ns. *3 : Minimum DC voltage on input or I/O pins are -0.3 V. During voltage transitions, inputs may undershoot VSS to -1.0 V for periods of up to 5 ns. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
PIN CAPACITANCE
(f = 1 MHz, TA = +25 C) Parameter Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance Symbol CIN1 CIN2 CIO Test conditions VIN = 0 V VIN = 0 V VIO = 0 V Value Min Typ Max 5 5 8 Unit pF pF pF
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MB82DP04184E-65L
ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(Under recommended operating conditions unless otherwise noted) Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage VDD Power Down Current Symbol ILI ILO VOH VOL IDDPS IDDP8 IDDP16 IDDS VDD Standby Current IDDS1 VSS VIN VDD VSS VOUT VDD, Output Disable VDD = VDD Min, IOH = -0.5 mA IOL = 1 mA VDD = VDD Max, VIN = VDD or VSS, CE2 = VSS VDD = VDD Max, VIN = VIH or VIL, CE1 = CE2 = VIH VDD = VDD Max, VIN = VDD or VSS, CE1 = CE2 = VDD VDD = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA VDD = VDD Max, VIN = VIH or VIL, CE1 = VIL and CE2 = VIH, IOUT = 0 mA, tPRC = Min TA + 85 C TA + 40 C tRC/tWC = Min tRC/tWC = 1 s Sleep 8M-bit Partial 16M-bit Partial Test conditions Value Min -1.0 -1.0 2.4 Max +1.0 +1.0 0.4 10 100 120 1.5 200 100 40 5 Unit A A V V A A A mA A A mA mA
IDDA1 VDD Active Current IDDA2
VDD Page Read Current
IDDA3
10
mA
Notes : * All voltages are referenced to VSS. * IDD depends on the output termination, load conditions, and AC characteristics. * After power on, initialization following power-up timing is required. DC characteristics are guaranteed after the initialization. * IDDPS, IDDP8, IDDP16, and IDDS1 might be higher for up to 600 ms after power-up or Power Down/standby mode entry.
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MB82DP04184E-65L
2. AC Characteristics
(1) Read Operation (Under recommended operating conditions unless otherwise noted) Parameter Read Cycle Time CE1 Access Time OE Access Time Address Access Time LB, UB Access Time Page Address Access Time Page Read Cycle Time Output Data Hold Time CE1 Low to Output Low-Z OE Low to Output Low-Z LB, UB Low to Output Low-Z CE1 High to Output High-Z OE High to Output High-Z LB, UB High to Output High-Z Address Setup Time to CE1 Low Address Setup Time to OE Low Address Invalid Time Address Hold Time from CE1 High Address Hold Time from OE High WE High to OE Low Time for Read CE1 High Pulse Width Symbol tRC tCE tOE tAA tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tAX tCHAH tOHAH tWHOL tCP Value Min 65 20 3 5 10 0 -6 10 -6 -6 10 10 Max 1000 65 40 65 30 20 1000 12 12 12 10 1000 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *10 *5, *8 *9 Notes *1, *2 *3 *3 *3, *5 *3 *3, *6 *1, *6, *7 *3 *4 *4 *4 *3 *3 *3
*1 : Maximum value is applicable if CE1 is kept at Low without change of address input of A21 to A3. *2 : Address should not be changed within minimum tRC. *3 : The output load 50 pF. *4 : The output load 5 pF. *5 : Applicable to A21 to A3 when CE1 is kept at Low. *6 : Applicable only to A2, A1 and A0 when CE1 is kept at Low for the page address access. *7 : In case page read cycle is continued with keeping CE1 stays Low, CE1 must be brought to High within 4 s. In other words, page read cycle must be closed within 4 s. *8 : Applicable when at least two of address inputs among applicable are switched from previous state. *9 : tRC(Min) and tPRC(Min) must be satisfied. *10 : If the actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may become longer by the amount of subtracting the actual value from the specified minimum value.
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MB82DP04184E-65L
(2) Write Operation (Under recommended operating conditions unless otherwise noted) Parameter Write Cycle Time Address Setup Time CE1 Write Pulse Width WE Write Pulse Width LB, UB Write Pulse Width LB, UB Byte Mask Setup Time LB, UB Byte Mask Hold Time Write Recovery Time CE1 High Pulse Width WE High Pulse Width LB, UB High Pulse Width Data Setup Time Data Hold Time OE High to CE1 Low Setup Time for Write OE High to Address Setup Time for Write Symbol tWC tAS tCW tWP tBW tBS tBH tWR tCP tWHP tBHP tDS tDH tOHCL tOES Value Min 65 0 40 40 40 -5 -5 0 10 10 10 12 0 -5 0 Max 1000 1000 1000 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *8 *9 *7 *7 Notes *1, *2 *3 *2, *3 *2, *3 *2, *3 *4 *5 *2, *6
*1 : Maximum value is applicable if CE1 is kept at Low without any address change. *2 : The sum of actual write pulse (tCW,tWP or tBW) and actual write recovery time (tWR) must be equal or greater than specified minimum tWC. *3 : Write pulse is defined from High to Low transition of CE1, WE, LB or UB, whichever occurs last. *4 : Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1 or WE whichever occurs last. *5 : Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE whichever occurs first. *6 : Write recovery is defined from Low to High transition of CE1, WE, LB or UB, whichever occurs first. *7 : Maximum values of tWHP and tBHP are applicable to Output Disable mode when CE1 = L, WE = OE = H after write operation. Refer to "(7) Write Timing 2 (WE Control)" in "TIMING DIAGRAMS". *8 : If OE is Low after minimum tOHCL, read cycle is initiated. In other words, OE must be brought to High within 5 ns after CE1 is brought to Low. *9 : If OE is Low after a new address input, read cycle is initiated. In other words, OE must be brought to High at the same time or before the new address valid.
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MB82DP04184E-65L
(3) Power Down Parameters (Under recommended operating conditions unless otherwise noted) Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1 High Hold Time following CE2 High after Power Down Exit [Sleep mode only] CE1 High Hold Time following CE2 High after Power Down Exit [not in Sleep mode] CE1 High Setup Time following CE2 High after Power Down Exit *1 : Applicable also to power-up. *2 : Applicable when Partial mode is set. (4) Other Timing Parameters (Under recommended operating conditions unless otherwise noted) Parameter CE1 High to OE Invalid Time for Standby Entry CE1 High to WE Invalid Time for Standby Entry CE2 Low Hold Time after Power-up CE1 High Hold Time following CE2 High after Power-up Input Transition Time Symbol tCHOX tCHWX tC2LH tCHH tT Value Min 5 5 50 300 1 Max 25 Unit ns ns s s ns *2 *1 Notes Symbol tCSP tC2LP tCHH tCHHP tCHS Value Min 10 65 300 70 0 Max Unit ns ns s ns ns *1 *2 *1 Notes
*1 : Some data might be written into any address location if tCHWX(Min) is not satisfied. *2 : The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5 ns, it may violate AC specification of some timing parameters. (5) AC Test Conditions Parameter Input High Voltage Input Low Voltage Input Timing Measurement Level Input Transition Time * AC Measurement Output Load Circuit
VDD 0.1 F VSS Device under Test 50 pF Output
Symbol VIH VIL VREF tT
Test Setup Between VIL and VIH
Value VDD x 0.8 VDD x 0.2 VDD x 0.5 5
Unit V V V ns
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MB82DP04184E-65L
TIMING DIAGRAMS
(1) Read Timing 1 (Basic Timing)
tRC
Address
tASC tCE
Address Valid
tCHAH tASC
CE1
tOE
tCP tCHZ
OE
tOHZ tBA
LB, UB
tBLZ tOLZ tOH tBHZ
DQ (Output)
tCLZ
Valid Data Output Note : This timing diagram assumes CE2 = H and WE = H.
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MB82DP04184E-65L
(2) Read Timing 2 (OE Control & Address Access)
tRC
tAX
tRC
Address
Address Valid
Address Valid
tAA tOHAH
tAA
CE1
Low tASO tOE
OE
LB, UB
tOHZ tOLZ tOH
Valid Data Output
tOH
Valid Data Output
DQ (Output)
Note : This timing diagram assumes CE2 = H and WE = H.
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MB82DP04184E-65L
(3) Read Timing 3 (LB , UB Byte Control Access)
tAX tRC tAX
Address
tAA
Address Valid
CE1, OE
Low
tBA
tBA
LB
tBA
UB
tBHZ tBLZ tOH tBLZ tBHZ tOH
DQ7 to DQ0 (Output)
Valid Data Output
tBLZ
Valid Data Output
tBHZ tOH
DQ15 to DQ8 (Output)
Valid Data Output
Note : This timing diagram assumes CE2 = H and WE = H.
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MB82DP04184E-65L
(4) Read Timing 4 (Page Address Access after CE1 Control Access)
tRC
Address (A21 to A3)
tRC
Address Valid
tPRC
Address Valid
tPRC
Address Valid
tPRC
Address Valid
Address (A2 to A0)
tASC
Address Valid
tPAA
tPAA
tPAA
tCHAH
CE1
tCE tCHZ
OE
LB, UB
tCLZ tOH tOH tOH tOH
DQ (Output)
Valid Data Output (Normal Access) Note : This timing diagram assumes CE2 = H and WE = H.
Valid Data Output (Page Access)
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MB82DP04184E-65L
(5) Read Timing 5 (Random and Page Address Access)
tRC
tAX
tRC
tAX
Address (A21 to A3)
tRC
Address Valid
tPRC
Address Valid
Address Valid
tRC
Address Valid
tPRC
Address Valid
Address (A2 to A0)
Address Valid
tAA
tPAA
tAA
tPAA
CE1
LOW
tASO
tOE
OE
tBA
LB, UB
tOLZ tOH tOH tOH tOH
DQ (Output)
tBLZ
Valid Data Output (Normal Access)
Valid Data Output (Page Access)
Notes : * This timing diagram assumes CE2 = H and WE = H. * Either or both LB and UB must be Low when both CE1 and OE are Low.
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MB82DP04184E-65L
(6) Write Timing 1 (Basic Timing)
tWC
Address
tAS
Address Valid
tCW tWR tAS
CE1
tCP tAS tWP tWR tAS
WE
tAS tWR
tWHP tBW tAS
LB, UB
tOHCL
tBHP
OE
tDS tDH
DQ (Input)
Valid Data Input Note : This timing diagram assumes CE2 = H.
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MB82DP04184E-65L
(7) Write Timing 2 (WE Control)
tWC
tWC
Address
Address Valid
Address Valid
tOHAH
CE1
Low tAS tWP tWR tAS tWP tWR
WE
tWHP
LB, UB
tOES
OE
tOHZ tDS tDH tDS tDH
DQ (Input)
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H.
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MB82DP04184E-65L
(8) Write Timing 3-1 (WE, LB, UB Byte Write Control)
tWC tWC
Address
Address Valid
Address Valid
CE1
Low tAS tWP tAS tWP
WE
tWR
tWHP tBS tBH
LB
tBS tBH tWR
UB
tDS tDH
DQ7 to DQ0 (Input)
tDS tDH
DQ15 to DQ8 (Input)
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H and OE = H.
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MB82DP04184E-65L
(9) Write Timing 3-2 (WE, LB, UB Byte Write Control)
tWC
tWC
Address
Address Valid
Address Valid
CE1
Low tWR tWR
WE
tAS tBW
tWHP tBS tBH
LB
tBH tAS tBW
tBS
UB
tDS tDH
DQ7 to DQ0 (Input)
tDS tDH
DQ15 to DQ8 (Input)
Valid Data Input
Valid Data Input Note : This timing diagram assumes CE2 = H and OE = H.
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MB82DP04184E-65L
(10) Write Timing 3-3 (WE, LB, UB Byte Write Control)
tWC
tWC
Address
Address Valid
Address Valid
CE1
Low
WE
tAS tBW tWR
tWHP tBH
tBS
LB
tBS tBH tAS tBW tWR
UB
tDS tDH
DQ7 to DQ0 (Input)
tDS tDH
DQ15 to DQ8 (Input)
Valid Data Input
Valid Data Input Note : This timing diagram assumes CE2 = H and OE = H.
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MB82DP04184E-65L
(11) Write Timing 3-4 (WE, LB, UB Byte Write Control)
tWC tWC
Address
Address Valid
Address Valid
CE1
Low
WE
tAS tBW tWR tBHP tDS tDH tDS tDH tAS tBW tWR
LB
DQ7 to DQ0 (Input)
tAS
Valid Data Input
tBW tWR tAS tBW
Valid Data Input
tWR
UB
tDS tDH
tBHP tDS tDH
DQ15 to DQ8 (Input)
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H and OE = H.
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MB82DP04184E-65L
(12) Read / Write Timing 1-1 (CE1 Control)
tWC
tRC
Address
tCHAH tAS
Write Address
tWR tCW tASC
Read Address
tCHAH tCE
CE1
tCP tCP
WE
UB, LB
tOHCL
OE
tCHZ tOH tDS tDH tCLZ tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : * This timing diagram assumes CE2 = H. * Write address is valid from either CE1 or WE of last falling edge.
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MB82DP04184E-65L
(13) Read / Write Timing 1-2 (CE1, WE, OE Control)
tWC
tRC
Address
tCHAH tAS
Write Address
tWR tASC
Read Address
tCHAH tCE
CE1
tCP tWP tCP
WE
UB, LB
tOHCL tOE
OE
tCHZ tOH tDS tDH tOLZ tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : * This timing diagram assumes CE2 = H. * OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read sequence.
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MB82DP04184E-65L
(14) Read / Write Timing 2 (OE, WE Control)
tWC
tRC
Address
Write Address
Read Address
tAA
tOHAH
tOHAH
CE1
Low tAS tWP tWR
WE
tOES
UB, LB
tASO tOE
OE
tOHZ tOH tDS tDH
tWHOL tOHZ tOLZ tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : * This timing diagram assumes CE2 = H. * CE1 can be tied to Low for WE and OE controlled operation.
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MB82DP04184E-65L
(15) Read / Write Timing 3 (OE, WE, LB, UB Control)
tWC
tRC
Address
Write Address
Read Address
tAA
tOHAH
tOHAH
CE1
Low
WE
tOES tAS tBW tWR tBA
UB, LB
tBHZ tASO
OE
tOH tDS tDH
tWHOL tBHZ tBLZ tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : * This timing diagram assumes CE2 = H. * CE1 can be tied to Low for WE and OE controlled operation. * Read data will be available after tAA from WE = H if read address are not changed from write address.
(16) Power-up Timing 1
CE1 tCHS tC2LH CE2 tCHH
VDD
0V
VDD (Min)
Note : The tC2LH specifies after VDD reaches specified minimum level.
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MB82DP04184E-65L
(17) Power-up Timing 2
CE1 tCHH CE2
VDD
0V
VDD (Min)
Note : The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1 and CE2. If transition time of VDD (from 0 V to VDD Min) is longer than 50 ms, " (16) Power-up Timing 1" must be applied.
(18) Power Down Entry and Exit Timing
CE1
tCHS
CE2
tCSP tC2LP tCHH (tCHHP)
DQ Power Down Entry
High-Z
Power Down Mode
Power Down Exit
Notes : * This Power Down mode can be also used as a reset timing if "Power-up timing" above could not be satisfied and Power Down program was not performed prior to this reset. * CE2 can be brought to Low after the completion of previous read/write operation. * CE2 must be kept at High during the specified minimum time of tCP.
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MB82DP04184E-65L
(19) Standby Entry Timing after Read or Write
CE1
tCHOX tCHWX
OE
WE Active (Read) Standby Active (Write) Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for standby mode.
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MB82DP04184E-65L
(20) Power Down Program Timing
tRC
tWC MSB*1
tWC MSB*1
tWC MSB*1
tWC MSB*1
tWC MSB*1
Address
MSB*1
tCP
tCP
tCP
tCP
tCP
tCP*3
CE1
OE
WE
LB, UB*4
DQ*3
RDa
RDa
RDa
FFFFh
Key*2
FFFFh
Cycle #1
Cycle #2
Cycle #3
Cycle #4
Cycle #5
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #6. *2 : The data key must conform to the format specified in " POWER DOWN". If not, the operation and data are not guaranteed. *3 : After tCP following Cycle #6, the Power Down program is completed and returned to the normal operation. *4 : Byte read or write is available in addition to word read or write. At least one byte control signal (LB or UB) needs to be Low.
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MB82DP04184E-65L
ORDERING INFORMATION
Part Number MB82DP04184E-65LTBG Package 71-ball plastic FBGA (BGA-71P-M03)
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MB82DP04184E-65L
PACKAGE DIMENSION
71-ball plastic FBGA Ball pitch Package width x package length Lead shape Sealing method Ball size Mounting height 0.80 mm 7.00 x 11.00 mm Soldering ball Plastic mold 0.45 mm 1.20 mm Max. 0.14 g
(BGA-71P-M03)
Weight
71-ball plastic FBGA (BGA-71P-M03)
11.000.10(.433.004)
0.20(.008) S B 1.09 .043
+0.11 -0.10 +.004 -.004
B (Seated height) 0.80(.031) REF A 0.40(.016) REF 0.80(.031) REF 8 7 6 5 4 3 2 1 MLKJHGFEDCBA
7.000.10 (.276.004)
0.40(.016) REF 0.10(.004) S
INDEX-MARK AREA S
0.390.10 (Stand off) (.015.004)
0.20(.008) S A
71-o0.45 +0.10 -0.05 +.004 71-o.018 -.002
o0.08(.003)
M
S AB
0.10(.004) S
C
2003 FUJITSU LIMITED B71003S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
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MB82DP04184E-65L
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
F0709

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